Patent Pending: Exit von Neumann? Not just yet
- By Jon William Toigo
- May 29, 2002
In the late 1990s, hopes were riding high for a move to virtual interface architecture, or VIA, inside the computer server. Advocates touted VIA as the first significant change to basic computer design since John von Neumann conceived the first one more than 50 years ago.
They envisioned a computer in which the function of a central processing unit would be divvied up among multiple, specialized CPUs, each performing a set of discrete functions such as networking, storage, graphics display, etc. The processors would interoperate across a high-performance serial interconnect called infiniband.
In short, the new server would be more like a network of computers inside a single chassis.
However, despite the often painful negotiation of vendor differences and scheduling of VIA products for release in the 2001, no one predicted the current economic malaise. December 2001 came and went without VIA, and the prevailing wisdom of the industry is that now is not the right time to foist an upgrade to a new server technology upon already economically beleaguered companies.
VIA and infiniband may have been put on the back burner, but not the problems that prompted their development. New applications, such as security and storage networking, are placing demands on CPU processing cycles and computer bus bandwidth that are quickly bringing servers to their knees.
As a stopgap, the industry is responding with "offload engines," specialized "daughterboards" (PCIx bus cards) that take a specific task, together with its processing burden, off the CPU and system bus.
Two examples are secure socket layer, or SSL, encryption acceleration products from nCipher Inc., and TCP/IP offload engines, or TOE, from Alacritech Inc., Intel Corp. and a growing list of storage networking vendors.
Woburn, Mass.-based nCipher.'s offload product targets the processing of SSL encryption key coding and decoding, removing the burden from the centralized CPU and thereby ensuring the dedication of CPU cycles to the real work of transaction processing.
According to vendor tests, nearly 95 percent of CPU processing cycles are consumed by SSL "handshaking" operations without the nCipher nForce Accelerator, compared to only 30 percent with the product. Company spokespersons claim that the improvements with SSL acceleration translate to a twentyfold increase in server processing capacity, so a lot more work can get done.
In the realm of storage networking, TOE technology has become all the rage. As TCP/IP comes into vogue as the connection of choice for linking servers to storage platforms in a storage area network, TOE is deemed critical by developers and analysts for the success of the strategy.
Today, as work is completed within the Internet Engineering Task Force on Small Computer Systems Interface over Internet Protocol (iSCSI), the vision of operating block storage across Internet protocol networks is coming closer to reality. This topology, however, requires the operation of SCSI, a very chatty protocol, across a frame-based network.
Today's servers, claim spokespersons from Emulex Corp., Alacritech and others, are not up to the job of processing so much network and storage input and output efficiently. Instead, these vendors offer host bus adapters equipped with TOE chips that offload TCP/IP and, in some cases, iSCSI processing itself.
While these examples merely work around the inefficiencies of a single-bus von Neumann machine, they do provide a bit more runway for existing computing platforms until the economy is right for the introduction of a next-generation architecture.Jon William Toigo is an independent consultant and author of more than 1,000 articles and 12 books. If there is an emerging technology you would like Jon to look at, contact him through www.toigoproductions.com or via e-mail at firstname.lastname@example.org.